1. Field of Invention
The present invention relates to an exposure transfer technique of a circuit pattern of a semiconductor integrated circuit, a flat-panel display (FPD), or the like, and more particularly, to a pattern forming technique of arranging dots or holes in a two-dimensional period.
2. Description of the Related Art
In recent years, miniaturization of a large scale integrated circuit (LSI) implemented by using semiconductors has been proceeding. As a result, in a lithography process, one of LSI manufacturing processes, pattern sizes have been miniaturized to the proximity of the resolution limit that is defined from the wavelength of a light source of an exposure device and the numerical aperture (NA) of a lens. A hole pitch (i.e., a distance between the centers of adjacent holes) in a hole pattern is closely related to a wiring pitch (i.e., a distance between the centers of a pair of adjacent wires), and, therefore, is largely linked to the pattern density. Accordingly, further miniaturization is demanded. As a method of forming such a narrow-pitched hole pattern, Japanese Patent Application Laid-Open No. 2002-287324, for example, proposes an exposure method by means of double exposure that uses a half-tone type phase shift mask and a normal photomask.